From a7c03190c35a86a8d41e19b4668ce89a1464fde8 Mon Sep 17 00:00:00 2001 From: Josuah Demangeon Date: Fri, 21 Jul 2023 10:49:38 +0200 Subject: [PATCH] new language name used by Minerva and RV32XXX -> `rv32xxx` Minerva switched to Amaranth: https://github.com/minerva-cpu/minerva/blob/main/minerva/core.py#L5-L6 from amaranth import * --- CPUs.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CPUs.md b/CPUs.md index 2c70542..544ecb6 100644 --- a/CPUs.md +++ b/CPUs.md @@ -16,7 +16,7 @@ Currently the supported Soft CPUs are: * [`vexriscv`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/vexriscv) -- an [FPGA Friendly RISC V core by SpinalHDL](https://github.com/SpinalHDL/VexRiscv), implementing the `rv32im` instruction set (hardware multiply optional) -* [`minerva`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/minerva) -- a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the [nMigen toolbox](https://github.com/m-labs/nmigen). +* [`minerva`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/minerva) -- a CPU core that currently implements the RISC-V `rv32im` instruction set with its microarchitecture described in plain Python code using the [Amaranth toolbox](https://github.com/amaranth-lang/amaranth/). * [`rocket`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/rocket) -- [Rocket Chip](https://github.com/chipsalliance/rocket-chip), a configurable, fully featured, 64-bit `rv64imafdc` capable core. @@ -275,7 +275,7 @@ A [small RISC V core by Clifford Wolf](https://github.com/cliffordwolf/picorv32) ## RISC-V - [`minerva`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/minerva) -The Minerva is a CPU core that currently implements the RISC-V RV32I instruction set with its microarchitecture described in plain Python code using the [nMigen toolbox](https://github.com/m-labs/nmigen). +The Minerva is a CPU core that currently implements the RISC-V `rv32im` instruction set with its microarchitecture described in plain Python code using the [Amaranth toolbox](https://github.com/amaranth-lang/amaranth). ### CPU Variants @@ -299,7 +299,7 @@ The Minerva is a CPU core that currently implements the RISC-V RV32I instruction ## RISC-V - [`rocket`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/rocket) -The Rocket Chip is a full-featured, configurable CPU core that implements up to the full RISC-V RV64IMAFDC (a.k.a. RV64GC) instruction set, with its microarchitecture described in [Chisel](https://github.com/freechipsproject/chisel3). +The Rocket Chip is a full-featured, configurable CPU core that implements up to the full RISC-V `rv64imafdc` (a.k.a. `rv64gc`) instruction set, with its microarchitecture described in [Chisel](https://github.com/freechipsproject/chisel3). ### CPU Variants @@ -347,4 +347,4 @@ The [NEORV32 RISC-V Processor](https://github.com/stnolting/neorv32) is a tiny, ### Community * [gitter channel](https://gitter.im/neorv32/community) - * community-driven [example setups and projects](https://github.com/stnolting/neorv32-setups) for various FPGAs, boards and toolchains \ No newline at end of file + * community-driven [example setups and projects](https://github.com/stnolting/neorv32-setups) for various FPGAs, boards and toolchains -- 2.41.0