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I am Josuah Demangeon

Projects

/software/ - /firmware/ - /hardware/ - /gateware/

Blog (atom)

2022-02-24: USB Standards

2022-04-22: Address decoding and multiplexer

2022-04-25: Wishbone B4: Standard or Pipelined?

2022-05-11: FPGA ←SPI→ MCU: Crossing Clock Domains

2022-05-12: Interacting with FPGA hardware

2022-05-18: Different Clock Domains With Verilator

2022-07-06: Interface in Open-Source SystemVerilog Synthesis

2022-07-08: SystemVerilog structs as ersatz to interafces

2022-07-20: Sequential signals may hide combinational ones

2022-07-22: Memes: #fpga #verilog #yosys #nextpnr